1. Field of the Invention
The present invention relates to a thin film semiconductor device and method for manufacturing the same.
The present application claims priority of Japanese Patent Application No. 2002-064795 filed on Mar. 11, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
Conventionally, in a CMOS (Complementary Metal Oxide Semiconductor)-type thin film semiconductor device, a gate electrode of an N (negative)-channel transistor and that of a P (positive)-channel transistor have been made of only a single metal material or only a single conductivity-type polysilicon material. By this method, however, a gate electrode material of the N-channel transistor and that of the P-channel transistor have a same work function, so that in order to give almost the same threshold voltage (Vth) to the two transistors, it has been necessary to extremely reduce a channel impurity concentration of either of the gate electrode materials of the N-channel transistor and the P-channel transistor.
Therefore, a thin film semiconductor device in which N-channel and P-channel transistors are formed on a polycrystal silicon on a glass substrate suffers from such disadvantages, owing to its process of a low-temperature treatment at 600° or less and a complexity of a surface orientation of the polycrystal silicon, that it has a large interface state density (which is typically 5×1011/cm2 versus 1×1011/cm2 of a monocrystal silicon) and also that the value of the Vth of either one of the two transistors that has a lower channel impurity concentration fluctuates greatly due to an influence of a fluctuation in interface state density. Accordingly, a voltage to drive a circuit cannot be reduced below a fluctuated maximum value of the Vth, so that it has been impossible to reduce the voltage to 2.5V or less, that is, to decrease power dissipation.
As methods to mitigate the above-mentioned fluctuations in the Vth there is reported an attempt disclosed in, for example, Japanese Patent Application Laid-open No. Hei 8-107153 by which in the case of monocrystal silicon, the gate polysilicon in the N-channel transistor is made an N (negative)-type and the gate polysilicon in the P-channel transistor is made a P (positive)-type to hereby utilize contribution of work functions of the gate electrodes or an attempt by which in the case of an SOI (Silicon on Insulator) construction, oppositely to the case of the monocrystal silicon, the gate polysilicon in the N-channel transistor is made a P-type and the gate polysilicon in the P-channel transistor is made an N-type to hereby utilize contribution of work functions of the gate electrodes.
However, although a-Si (amorphous silicon) which is formed on the glass substrate and polycrystallized with excimer laser or a like has normally a positive interface state density and so it is necessary to reduce the Vth by making the N-type of the gate polysilicon in the N-channel transisitor, and the P-type of the gate polysilicon in the P-channel transisitor oppositely to the case of an SOI construction disclosed in Japanese Patent Application Laid-open No. Hei 8-107153, it is impossible to mitigate fluctuations in the Vth sufficiently only by utilizing the work functions of the gate electrodes.
Supposing, for example, that a film thickness of a gate oxide film is 50 nm and its interface state density (QSS) is 5×1011/cm2, a channel impurity concentration required to obtain a Vth value of 2V or less is about 2.1×1016/cm3 for the P-channel type and about 1.8×1017/cm3 for the N-channel type, which indicates that an almost sufficient channel impurity concentration can be obtained for the N-channel type but, for the P-channel type, as compared to the case of the monocrystal Si, the channel impurity concentration cannot be regarded to be sufficient as compared with a very large QSS value of about 5×1011/cm2 and so a fluctuation (standard deviation) in the Vth exceeds 0.3V, so that it is eventually very difficult to apply the above-mentioned methods to a low-voltage circuit which operates on 2.5V or less.